1. Technical Field
The present invention relates generally to a comparator and, more particularly, to a CMOS comparator with hysteresis.
2. Description of Related Art
In general, a comparator is a device which compares an input voltage with a reference voltage, amplifies the voltage differential between the input voltage and the reference voltage, and outputs a voltage signal of a high or low level based on the voltage differential. A comparator is typically employed in an analog-digital converter (such as a flash A/D converter), wherein an analog input signal is converted to a digital output signal by comparing the analog input signal with a plurality of reference voltages by using a complimentary metal-oxide semiconductor (CMOS) flash analog-digital converter.
Because of their high speed, flash analog-digital converters are widely employed in video devices, radar devices, laboratory instruments, and other devices which are used in high-speed applications. Other advantages associated with CMOS flash analog-digital converters are their compact size and low power dissipation, which enables them to be fabricated as monolithic integrated circuits.
For the comparator output voltage to be maintained at a high level state at a zero point, hysteresis is used to prevent the output voltage from changing as the input voltage is reduced. When the input voltage drops to a lower reference voltage (a negative trip point), the output voltage changes from the high level state to a low level state. The comparator output voltage will remain in the low level state as the input voltage increases. When the input voltage reaches an upper reference voltage (a positive trip point), the output voltage will change from the low level state to the high level state. The difference in voltage between the upper reference voltage and the lower reference voltage is known as the amount of the hysteresis. It is to be understood that the terms "high level state" (or "high") and "low level state" (or "low") used herein in connection with signals and logic levels are equivalent to logic levels "1" and "0", respectively.
Referring to FIG. 1, a circuit diagram illustrates a conventional comparator with hysteresis. Although there are many techniques known by those skilled in the art for providing hysteresis in a comparator, all of the conventional techniques employ some form of positive feedback. Consider the differential input stage as shown in FIG. 1. In this circuit, there are two feedback paths. The first feedback path is a current-series feedback through the common-source node of transistors M1 and M2, which is a negative feedback path. The second feedback path is the voltage-shunt feedback through the gate-drain connections of transistors M10 and M11, which is a positive feedback path. It is understood by those skilled in the art that if the positive feedback factor is less than the negative feedback factor, the overall feedback will be negative, thus resulting in no hysteresis. On the other hand, If the positive feedback factor is greater than the negative feedback factor, the overall feedback will be positive, which results in hysteresis (such as illustrated by the voltage transfer curve of FIG. 5).
A comparator is typically employed in a noisy environment, thereby requiring hysteresis to ensure a noise margin. With the conventional comparator shown in FIG. 1, the desired amount of hysteresis can be determined in accordance with the ratio of size of MOS transistors. Unfortunately, in order to control the trip voltages (and, therefore, the amount of the hysteresis), the comparator must be entirely reconstructed or an additional process is required for changing the ratio of size of transistors. As a result, it difficult to control the amount of the hysteresis. Another problem is that the conventional comparator also includes bias circuitry, which adds to the difficulty in controlling the amount of hysteresis.